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Associate Professor Ankur Srivastava (ECE/ISR) and Associate Professor Donald Yeung (ECE) have won a three-year, $500K grant for ?Developing and Applying Reuse Distance Analysis Techniques for Large-Scale Multi-core Processors.? The award is being funded through the National Science Foundation?s Software and Hardware Foundations (SHF) program within the Division of Computing and Communication Foundations (CCF). Yeung is the principal investigator.
The research will address concerns in multi-core and many-core architecture by exploring research directions related to multi-core reuse distance (RD) analysis for loop-based parallel programs.
Today, simulation is the de facto method for studying multi-core cache hierarchies. But simulation is costly due to the combinatorial design spaces involved, especially as multi-core processors scale to 100s of cores and 100+ MB of on-chip cache. RD analysis can help architects evaluate multi-core memory performance more efficiently.
The research will characterize how concurrent RD and per-thread RD profiles for symmetric threads vary with processor and problem scaling and develop techniques to predict these profile variations. Simple prediction techniques such as reference groups, as well as more sophisticated parametric and non-parametric learning approaches will be studied. By applying the new RD analyses to explore large-scale multi-core design spaces, good cache hierarchy organizations will be identified. The RD analyses will incite improvements to existing memory performance enhancement techniques such as multithreading and locality optimization.
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July 28, 2011
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